1. Field of the Invention
The invention generally relates to input/output devices and, more particularly, relates to input/output devices for controlling input/output in a separate-type input/output (hereinafter referred to as "I/O") system and an operating method thereof.
2. Description of the Background Art
There are a separate-type I/O system (I/O mapped I/O system) and a memory mapped I/O system in input/output systems of microprocessors. FIG. 10 shows an address space in an I/O mapped I/O system and FIG. 11 shows an address space in a memory mapped I/O system.
As shown in FIG. 10, memories are arranged in a memory space and input/output devices (hereinafter referred to as "I/O devices") are arranged in an I/O space in the I/O mapped I/O system. As shown in FIG. 11, I/O devices are arranged in a part of the region on the memory space in the memory mapped I/O system.
FIG. 12 is a block diagram showing a structure of an I/O mapped I/O system containing conventional I/O devices.
I/O devices 100 and memories 300 are connected to a central processing unit (hereinafter referred to as "CPU") 200 through a data bus DB, an address bus AB and a control bus CB. An identification signal M/I supplied from CPU200 is applied to a decoder 400 through an inverter G4. A plurality of output signals of decoder 400 are supplied to I/O devices 100 as chip select signals CS. An identification signal M/I supplied from CPU200 is applied to a decoder 500. A plurality of output signals of decoder 500 are supplied to memories 300 as chip select signals CS, respectively.
Address signals A15-A4 are supplied to decoder 400 and address signals A3-A0 are supplied to I/O devices 100. Address signals A19-A10 are supplied to decoder 500 and address signals A9-A0 are supplied to memories 300. Addresses within the I/O space designated by the address signals A15-A0 are thereby assigned to I/O devices 100, and addresses within the memory space designated by the address signals A19-A0 are assigned to memories 300.
The identification signal M/I is used for identifying whether address signals on address bus AB indicate an address on the I/O space or an address on the memory space. Either of decoder 400 and decoder 500 is activated in response to the identification signal M/I. The output signal of decoder 400 activates any one of I/O devices 100. The output signal of decoder 500 activates any one of memories 300.
An external equipment such as a printer, a keyboard, and a communication line is connected to I/O devices 100. Since the operation speed of the external equipment is normally different from that of CPU200, each of I/O devices 100 has a register for temporarily storing data to be transmitted to the external equipment and data received from the external equipment. Each of I/O devices 100 functions as an interface between CPU200 and the external equipment.
Data supplied from CPU200 or data read out from memories 300 through CPU200 is transmitted to the registers within I/O devices 100 through data bus DB and temporarily stored therein. The stored data is transmitted to the external equipment.
Data received from the external equipment is temporarily stored in the registers within I/O devices 100. The stored data is transmitted to CPU200 through data bus DB or to memories 300 through CPU200. I/O devices 100 are controlled by a control signal supplied from CPU200 through control bus CB.
It is necessary to increase the storage capacity of the register included in each of I/O devices 100 in order to increase the amount of data to be inputted to/outputted from the external equipment in the I/O mapped I/O system as stated above. The I/O space, however, is generally smaller than the memory space.
Additionally, even if the I/O space is large, the software thereof becomes complicated in order to access the large I/O space.
Furthermore, if the storage capacity of the registers within I/O devices 100 is small, when a large amount of data is to be transmitted to the external equipment, the data needs to be transmitted many times from CPU200 or memories 300 through data bus DB. Data bus DB cannot be used for other processing during the data transmission.